The present invention relates to techniques for transmitting and receiving SPI4.2 status signals using a hard intellectual property (HIP) block, and more particularly, to techniques for reducing the number of input and output ports required to receive and transmit SPI4.2 status signals on a HIP block.
The convergence of systems used in LAN, WAN, MAN, and SAN segments require new, interoperable communications technologies. Modular equipment must have flexible architectures that can support multiple protocols, including Ethernet for the LAN, SONET/SDH for the MAN/WAN, and Fiber Channel for the SAN.
System Packet Interface Level 4, Phase 2 (SPI4.2) is an electrical interface specification for complex communications systems that allows packet and cell transfer between a physical layer device and a link layer device. SPI4.2 allows communications systems to transmit multiple communications protocols using variable, high speed, data rates of up to 10 Giga bytes per second (Gbps), including Packet over SONET/SDH (POS), OC-192, Ethernet, Fast Ethernet, Gigabit Ethernet, 10 GbE, and 10G SAN.
The SPI4-2 interface specification stipulates 16 bit wide transmitter and receiver data paths. The SPI4-2 interface specification also stipulates 2 bit wide FIFO status information is sent and received separately from the corresponding data path. The status information can be sent/received at either ⅛th of the SPI4.2 data rate, or at the SPI4.2 data rate (hereby known as ‘full rate’). A SPI4.2 system contains a transmitter data interface and a receiver data interface. The FIFO status information is transmitted separately from the corresponding paths that are used to transmit data. By taking the FIFO status information out-of-band, it is possible to decouple the transmit and receive interfaces so that each operates independently of the other.
As data comes in and out of the FIFO, FIFO status information is relayed to the interface. The FIFO status information indicates how much more data a first-in-first-out (FIFO) buffer associated with an input port can store. The FIFO status of each port/calendar slot is encoded in a 2-bit data structure. The 2-bit data structure indicates one of three status values (satisfied, hungry, or starving) with respect to a port's FIFO. A FIFO status value associated with a port indicates how much data can be transmitted to that port. The FIFO status values are sent to a data transmitter and processed in a calendar portion of a FIFO status state machine.
The FIFO status information is decoded using the calendar portion of a FIFO status state machine associated with the transmitter. In response, the transmitter transmits an appropriate amount of data to the receiving port.
Programmable logic devices (PLDs) are a type of programmable logic integrated circuit. Programmable logic integrated circuits can be configured to perform a variety of logical user functions. Programmable logic integrated circuits also include field programmable gate arrays (FPGAs), programmable logic arrays, configurable logic arrays, etc. Many of today's programmable logic integrated circuits (ICs) have on-chip non-programmable application specific integrated circuit (ASIC) blocks that are referred to as hard intellectual property (HIP) blocks.
Many of today's applications for communications systems require programmable logic integrated circuits, because PLDs and FPGAs provide user design flexibility that is not provided by application specific integrated circuits (ASICs). For example, it may not make economic sense to design and mass produce an ASIC for a low volume communications system. SPI4.2 transmitter and receiver interfaces can be implemented in programmable logic circuits. However, a comparable programmable logic implementation uses more than 2× amounts of logic gates, and at least 2× more time to process the data (system latency).
A complete SPI4.2 HIP implementation features a FIFO status interface for sending and receiving SPI4.2 FIFO status information. Therefore, it would be desirable to provide a SPI4.2 status interface in a HIP block on a programmable logic IC that saves programmable logic resources, uses as few HIP I/O resources as possible, while providing adequate status transfer throughput to keep up with a full-rate SPI4.2 status channel implementation.